🔌 Computer Clock Logic Circuit Simulator

Interactive logic gate simulation (Ben Eater Computer Clock - Part 4)

⏱️ Clock Mode
Select Mode

ON = Astable (Auto) | OFF = Manual

👆 Manual Pulse

Active in Manual mode only

🛑 Halt Control
Halt Signal

ON = Computer Halted

Logic Gate Circuit Flow
💡 Final Clock Output
LOW
Astable Pulse
0
Manual Pulse
0
Select
0
Halt
0
📚 How the Logic Works:
AND Gates: Both inputs must be HIGH (1) for output to be HIGH.
OR Gate: At least one input must be HIGH for output to be HIGH.
Inverter (NOT): Flips the signal (1 → 0, 0 → 1).

When Select is ON, the astable clock pulses pass through AND gate #1 to the OR gate, while the manual pulse path is blocked by AND gate #2 (due to inverted Select).

When Select is OFF, manual pulses pass through AND gate #2, while the astable path is blocked.

The Halt signal uses the final AND gate to stop all clock pulses when activated, preventing the computer from executing any further instructions until reset.