🗺 Binary / Hex Memory Map Converter

Ben Eater 6502 Series — Video 6: RAM and Bus Timing — Address Decode Logic

16-Bit Address Bus

A15 – A12  (HIGH BYTE HI)
A11 – A8   (HIGH BYTE LO)
A7 – A4    (LOW BYTE HI)
A3 – A0    (LOW BYTE LO)

Chip Select / Output Enable Logic

Address Decode Truth Table

A15 A14 A13 Region Range Size
Mapped Region
RAM
$0000 – $3FFF

64K Memory Map

How the Decode Works

A15 → CS* of 62256 RAM (via NAND/inverter)

A14 → OE* of 62256 RAM (tied directly)

RAM active only when both A15=0 and A14=0

A15 → CS* of ROM (active-high)

I/O uses A15=0, A14=1, A13=1 for VIA 6522

RAM Chip 62256

32 KB — but only 16 KB used (0000–3FFF)

Tying OE* to A14 prevents RAM from driving the bus above 3FFF, keeping address decode simple and avoiding bus conflicts.